In a DRAM multiple-bit-level storage design described in U.S. Pat. No. 5,283,761, invented by Peter Gillingham, a voltage stored in a memory cell may be one of four levels. To read the stored voltage, charge stored in the memory cell is dumped onto a bitline to create a data voltage, and the data voltage is sensed relative to a first reference voltage to provide a sign bit and relative to a second reference voltage, determined by the sign bit, to provide a magnitude bit. The first reference is a voltage level midway between a highest and a lowest of four levels. The second reference voltage is set to be higher than the lowest and lower than the next highest of the four levels in the event that the data voltage is below the midway voltage level, and set to a voltage higher than the second highest and lower than the highest of the four levels in the event that the data voltage is above the midway point. To that end, a high level charge dependent on the sensed sign bit and stored on a dummy capacitor matching a storage capacitor is dumped onto three bitlines and onto a capacitor of half the capacitance of the storage capacitor. The data voltage is then sensed as to whether it is higher or lower in voltage than the dumped voltage on a reference bitline (providing the magnitude bit), whereby the data bit is read as one of the four levels.
To restore the charge to the memory cell, either a full logic level is written to the cell, or an attenuated version thereof, depending on whether the data voltage was either the highest or lowest, or the second lowest or second highest values respectively. This required a circuit which attenuated a voltage conditionally based on the value of sensed data. Such a circuit is difficult to implement in the tight pitch of a DRAM sense amplifier.
The description of U.S. Pat. No. 5,283,761 is incorporated herein by reference.